A RAM (Random Access Memory) macro that performs a predetermined process in synchronization with a clock may generate phase clocks that are used inside the RAM macro in accordance with an external clock in some cases, for example, in order to perform pipeline processing inside the RAM macro (see Japanese Laid-open Patent Publication No. 2002-158286). The RAM macro is a circuit configured to perform a predetermined process and is mounted on a chip such as CPU (Central Processing Unit).
For example, the external clock is classified into two phase clocks, the phase clocks are respectively referred to as a phase 1 clock (hereinafter, “ph1”) and a phase 2 clock (hereinafter, “ph2”), and predetermined processes are assigned to the respective phase clocks. For example, the writing of data and the reading of data are performed at ph1 and the control of word line and the control of memory cell are performed at ph2. When RAM macros as described above are mounted on a chip, such as a CPU, switching between ph1 and ph2 is performed on all the RAM macros in the same manner in many cases because of the convenience of clock distribution and CPU setting.